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ltc6903/ltc6904 1 69034fe typical a pplica t ion fea t ures a pplica t ions descrip t ion 1khz to 68mhz serial port programmable oscillator the lt c ? 6903/ltc6904 are low power self contained digital frequency sources providing a precision frequency from 1khz to 68 mhz, set through a serial port. the ltc6903/ ltc6904 require no external components other than a power supply bypass capacitor, and they operate over a single wide supply range of 2.7v to 5.5v. the ltc6903/ ltc6904 feature a proprietary feedback loop that linearizes the relationship between digital control set- ting and frequency, resulting in a very simple frequency setting equation: f hz da c khzf mh z oc t = ? ? ? ? ? ? << 2 2078 2 1024 16 8 ? () ? ; where oct is a 4- bit digital code and dac is a 10-bit digital code. the ltc6903 is controlled by a convenient spi compatible serial interface. the ltc6904 uses an industry standard i 2 c compatible interface. a microcontroller controlling its clock n precision digitally controlled oscillator n power management n direct digital frequency synthesis (dds) replacement n replacement for dac and vco n switched capacitor filter clock n 1khz to 68mhz square wave output n 0.5% (ty p ) initial frequency accuracy n frequency error <1.1% over all settings n 10ppm/c typical frequency drift over t emperature n 0.1% resolution n 1.7 ma typical supply current (f < 1mhz, v s = 2.7v) n 2.7v to 5.5v single- supply operation n jitter <0.4% typical 1khz to 8mhz n easy to use spi (ltc6903) or i 2 c (ltc6904) serial interface n output enable pin n C55c to 125c operation n ms8 package pic16f73 microcontroller v dd v ss rc2/ccp1 v ss rc5/sdo rc3/sck/scl ltc6903 0.01f gnd sdi sck sen power-up clock frequency is 1039hz v + 5v 10 10k 5v oe clk 69034 ta01 clk osc2/clkout osc1/clkin mclr/v p?p 1f 0.1f frequency error (%) ?1.0 units 40 30 20 10 0 ?0.5 69034 ta01b 0 0.5 1.0 v s = 3v t a = 25c f = 1039hz 443 units tested ltc6903 frequency error distribution l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 6342817 and 6614313.
ltc6903/ltc6904 2 69034fe a bsolu t e maxi m u m r a t ings total supply voltage (v + to gnd ) ................................ 6 v maximum voltage on any pin ............. ( gn d C 0.3 v) v pin (v + + 0.3 v) output short - circuit duration ( note 2) ............ ind efinite operating temperature range ( note 3) ltc 6903 cms 8/ ltc 6904 cms 8 ............ C 40 c to 85 c ltc 6903 ims 8/ ltc 6904 ims 8 .............. C 40 c to 85 c ltc 6903 hms 8/ ltc 6904 hms 8 ......... C 40 c to 125 c ltc 6904 mpms 8 ............................... C 55 c to 125 c specified temperature range ( note 4) ltc 6903 cms 8/ ltc 6904 cms 8 ................ 0 c to 70 c ltc 6903 ims 8/ ltc 6904 ims 8 .............. C 40 c to 85 c ltc 6903 hms 8/ ltc 6904 hms 8 ......... C 40 c to 125 c ltc 6904 mpms 8 ............................... C 55 c to 125 c storage temperature range .................. C 65 c to 150 c lead temperature ( soldering , 10 sec ) ................... 30 0 c (note 1) 1 2 3 4 gnd sdi sck sen/adr* 8 7 6 5 v + oe clk clk top view ms8 package 8-lead plastic msop t jmax = 150c, ja = 200c/w *sen (ltc6903) adr (ltc6904) o r d er i n f or m a t ion lead free finish tape and reel part marking* package description specified temperature range ltc6903cms8#pbf ltc6903cms8#trpbf ltabn 8-lead plastic msop 0c to 70c ltc6903ims8#pbf ltc6903ims8#trpbf ltabn 8-lead plastic msop C40c to 85c ltc6903hms8#pbf ltc6903hms8#trpbf ltabn 8-lead plastic msop C40c to 125c ltc6904cms8#pbf ltc6904cms8#trpbf ltaes 8-lead plastic msop 0c to 70c ltc6904ims8#pbf ltc6904ims8#trpbf ltaes 8-lead plastic msop C40c to 85c ltc6904hms8#pbf ltc6904hms8#trpbf ltaes 8-lead plastic msop C40c to 125c ltc6904mpms8#pbf ltc6904mpms8#trpbf ltfdx 8-lead plastic msop C55c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ p in c on f igura t ion
ltc6903/ltc6904 3 69034fe p ower r equire m en t s the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v + = 2.7v to 5.5v, gnd = 0v, unless otherwise noted. symbol parameter conditions min typ max units v s supply voltage applied between v + and gnd l 2.7 5.5 v i s , shdn v + supply current, shutdown v s = 2.7v v s = 5.5v l l 0.25 0.6 0.6 2.2 ma ma i s , dc v + supply current, single output enabled f = 68mhz, 5pf load, v + = 2.7v f < 1mhz, v + = 2.7v f = 68mhz, 5pf load, v + = 5.5v f < 1mhz, v + = 5.5v l l l l 3.6 1.7 7 1.9 7 3.1 15 4.5 ma ma ma ma e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v + = 2.7v to 5.5v, gnd = 0v, unless otherwise noted. symbol parameter conditions min typ max units ?fi initial frequency accuracy f = 1.039khz, v + = 3v, c load = 5pf 0.75 % ?f total frequency accuracy (note 7) single output active: over all settings, v + = 2.7v, c load = 5pf over all settings, v + = 5.5v, c load = 5pf 0.5 0.5 1.1 1.6 % % ltc6903cms8, ltc6904cms8: over all settings, v + = 2.7v, c load = 5pf over all settings, v + = 5.5v, c load = 5pf l l 0.5 0.5 1.65 2 % % ltc6903hms8, ltc6903ims8, ltc6904hms8, ltc6904ims8, ltc6904mpms8: over all settings, v + = 2.7v, c load = 5pf over all settings, v + = 5.5v, c load = 5pf l l 0.5 0.5 1.9 2.2 % % f max maximum operating frequency 68 mhz f min minimum operating frequency 1.039 khz ?f/?t frequency drift over temperature 10 ppm/c ?f/?v frequency drift over supply 0.05 %/v long-term frequency stability 300 ppm/khr timing jitter (see graph) 1.039khz to 8.5mhz 1.039khz to 68mhz 0.4 1 % % duty cycle 1.039khz to 1mhz 1.039khz to 68mhz l 49 50 50 51 % % r out output resistance clk, clk pins, v + = 2.7v 45 v oh high level output voltage v + = 5.5v, 4ma load v + = 2.7v, 4ma load l l 4.8 2 5.3 2.3 v v v + = 5.5v, 1ma load v + = 2.7v, 1ma load l l 5.2 2.3 5.45 2.55 v v v ol low level output voltage v + = 5.5v, 4ma load v + = 2.7v, 4ma load l l 0.15 0.25 0.3 0.45 v v v + = 5.5v, 1ma load v + = 2.7v, 1ma load l l 0.05 0.05 0.15 0.2 v v t r output rise time (10% - 90%) v + = 5.5v, r load = , c load = 5pf v + = 2.7v, r load = , c load = 5pf 1 1 ns ns t f output fall time (10% - 90%) v + = 5.5v, r load = , c load = 5pf v + = 2.7v, r load = , c load = 5pf 1 1 ns ns
ltc6903/ltc6904 4 69034fe symbol parameter min typ max units ltc6903 (notes 5, 6) f sck serial port clock frequency l 20 mhz t ckhi min clock high time l 25 ns t cklo min clock low time l 25 ns t su min setup time C sdi to sck l 10 ns t hld min hold time C sck to sdi l 10 ns t lch min latch time C sen to sen l 400 ns t fck min first clock C sen to sck l 20 ns ltc6904 (notes 5, 6) f smb smbus operating frequency l 10 100 khz t buf bus free time between stop and start condition l 4.7 s t hd, sta hold time after (repeated) start condition l 4.0 s t su, sta repeated start condition setup time l 4.7 s t su,sto stop condition setup time l 4.0 s ltc6904 (notes 5, 6) t hd, dat data hold time l 300 ns t su, dat data setup time l 250 ns t low clock low period l 4.7 s t high clock high period l 4.0 50 s t f clock, data fall time l 300 ns t r clock, data rise time l 1000 ns ti m ing c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v + = 2.7v to 5.5v, gnd = 0v, unless otherwise noted. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: a heat sink may be required to keep the junction temperature below the absolute maximum when the output is shorted indefinitely. note 3: the ltc6903cms8, ltc6904cms8, ltc6903ims8 and ltc6904ims8 are guaranteed functional over the operating temperature range of C40c to 85c. note 4: the ltc6903cms8 and ltc6904cms8 are guaranteed to meet the specified performance limits over the 0c to 70c temperature range and are designed, characterized and expected to meet the specified performance from C40c to 85c but are not tested or qa sampled at these temperatures. the ltc6903ims8 and ltc6904ims8 are guaranteed to meet the specified performance limits over the C40c to 85c temperature range. the ltc6903hms8 and ltc6904hms8 are guaranteed to meet the specified performance limits over the C40c to 125c temperature range. the ltc6904mpms8 is guaranteed to meet the specified performance limits over the C55c to 125c temperature range. note 5: all values are referenced to v ih and v il levels. note 6: guaranteed by design and not subject to test. note 7: parts with tighter frequency accuracy are available. consult lt c marketing for details. s erial p or t e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, other wise specifications are at t a = 25c. v + = 2.7v to 5.5v, gnd = 0v, unless otherwise noted. symbol parameter conditions min typ max units v ih min high level input voltage sen, sck, sdi pins l 0.67 v + v v il max low level input voltage sen, sck, sdi pins l 0.33 v + v i in digital input leakage sen, sck, sdi pins l 10 a
ltc6903/ltc6904 5 69034fe typical p er f or m ance c harac t eris t ics integral nonlinearity dac setting 0 200 400 600 800 1000 integral nonlinearity (lsb) 69034 g01 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 dac setting 0 200 400 600 800 1000 differential nonlinearity (lsb) 69034 g01 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 temperature (c) ?40 ?20 0 20 40 60 80 120100 frequency (%) 69034 g03 0.10 0.06 0.02 0.08 0.04 0 ?0.02 ?0.04 ?0.06 ?0.08 ?0.10 differential nonlinearity frequency vs temperature peak-to-peak jitter vs frequency supply current vs output frequency output resistance vs supply voltage output spectrum at 20mhz output waveform at 68mhz output waveform at 20mhz frequency (mhz) 0.1 1 10 100 peak-to-peak jitter (%) 69034 g04 10 1 0.1 0.01 v + = 3v frequency (mhz) 0.001 0.01 0.1 1 10 100 supply current (ma) 69034 g05 10 8 9 7 5 3 6 4 2 1 0 v + = 3v v + = 5v supply voltage (v) 3.5 4.5 2.5 3.0 4.0 5.0 5.5 output resistance () 69034 g06 60 50 40 30 20 10 0 15mhz 25mhz 10db/div 69034 g07 20 0 ?80 20mhz 0.5/div 5ns/div 69034 g08 c l = 10pf v + = 3v 0.5/div 10ns/div 69034 g08 c l = 10pf v + = 3v
ltc6903/ltc6904 6 69034fe p in func t ions gnd (pin 1): negative power supply ( ground). should be tied directly to a ground plane for best performance. sdi (pin 2): serial data input. data for serial transfer is presented on this pin. sck (pin 3): serial port clock. input, positive edge trig- gered. clocks serial data in on rising edge. sen ( pin 4): serial port enable (ltc6903 only). input , active low. initiates serial transaction when brought low, finalizes transaction when brought high after 16 clocks. adr (pin 4): serial port address ( ltc6904 only). sets the i 2 c serial port address. clk (pin 5): auxiliary clock output. frequency set by serial port. clk ( pin 6): main clock output. frequency set by serial port. oe (pin 7): asynchronous output enable. clk and clk are set low when this pin is low. v + ( pin 8): positive power supply. this supply must be kept free from noise and ripple. it should be bypassed directly to a ground plane with a quality 0.1 f capacitor. additional bypass may be necessary for operation at high frequency or under larger loads. b lock diagra m 2 1 3 4 6 7 5 8 ? + master oscillator f mo = 68mhz ? k i set v + ? v set programmable divider + ? i set v set a1 serial port v + oe gnd dac oct sdi sck sen (ltc6903) adr (ltc6904) clk clk 69034 bd
ltc6903/ltc6904 7 69034fe ti m ing diagra m s ltc6904 timing diagram ltc6904 typical input waveform programming frequency to 68mhz (adr pin set low) ltc6903 timing diagram sen sdi sck d15 d14 d13 d12 d11 d10 d8 d9 d7 d6 d5 d4 d3 d2 d1 d0 69034 td01 t su, dat t hd, sta t hd, dat sda scl t su, sta t hd, sta t su, sto 69034 td02 t buf t low t high start condition repeated start condition stop condition start condition t r t f ack 1 2 3 address 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 69034 td03 0 0 1 0 1 1 1 0 0 0 1 0 1 1 adr wr 1 1 1 1 1 1 1 1 oct3 oct2 oct1 oct0 dac9 dac8 dac7 dac6 1 1 1 1 1 1 0 0 dac5 dac4 dac3 dac2 dac1 dac0 cnf1 cnf0 ack stop start sda scl ack
ltc6903/ltc6904 8 69034fe theory o f o pera t ion a pplica t ions i n f or m a t ion the ltc6903/ltc6904 contain an internal feedback loop which controls a high frequency square wave vco oper- ating between 34mhz and 68mhz. the internal feedback loop frequency is set over an octave by a 10- bit resistor dac. the vco tracks the internal feedback loop frequency and the output frequency of the vco is divided by one of sixteen possible powers of two. higher vco frequencies and lower output divider settings can result in higher output jitter. random jitter at the lower frequency ranges is very low because of the high output divisor. the higher frequency settings will display some deter- ministic jitter from coupling between the control loop and the output. this shows up in the frequency spectrum as spurs separated from the fundamental frequency by 1mhz to 2mhz. frequency setting information the frequency output of the ltc6903/ltc6904 is deter- mined by the following equation: f hz dac oct = ? ? ? ? ? ? 2 2078 2 1024 ? () ? where dac is the integer value from 0-1023 represented by the serial port register bits dac[9:0] and oct is the integer value from 0-15 represented by the serial port register bits oct [3:0]. use the following two steps to choose binary numbers oct and dac in order to set frequency f: 1) use table 1 to choose oct or use the following formula, rounding down to the integer value less than or equal to the result. oct f = ? ? ? ? ? ? 3 322 1039 . log 2) choose dac by the following formula, rounding dac to the nearest integer: dac = 2048 C 2078(hz) ? 2 (10 + oct) f for example, to set a frequency of 6.5 mhz, first look at table 1 to find an oct value . 6.5 mhz falls between 4.25mhz and 8.5 mhz yielding an oct value of 12 or 1100. substituting the oct value of 12 and the desired frequency of 6.5 mhz into the previous equation results in: dac = 2048 C 2078(hz) ? 2 (10 + 12) 6.5e6(hz) = 707.113 rounding 707.113 to the nearest integer yields a dac value of 707 (or a 10-bit digital word of 1011000011.) table 1. output frequency range vs oct settling (frequency resolution 0.001 ? f) f f < oct 34.05mhz 68.03mhz 15 17.02mhz 34.01mhz 14 8.511mhz 17.01mhz 13 4.256mhz 8.503mhz 12 2.128mhz 4.252mhz 11 1.064mhz 2.126mhz 10 532khz 1063khz 9 266khz 531.4khz 8 133khz 265.7khz 7 66.5khz 132.9khz 6 33.25khz 66.43khz 5 16.62khz 33.22khz 4 8.312khz 16.61khz 3 4.156khz 8.304khz 2 2.078khz 4.152khz 1 1.039khz 2.076khz 0
ltc6903/ltc6904 9 69034fe applica t ions in f or m a t ion power-up state when power is first applied to the ltc6903/ltc6904, all register values are automatically reset to 0. this results in an output frequency of 1.039khz with both outputs active. output spectrum in most frequency ranges, the output of the ltc6903/ ltc6904 is generated as a division of the higher internal clock frequency. this helps to minimize jitter and sub- harmonics at the output of the device. in the highest frequency ranges, the division ratio is reduced, which will result in greater cycle-to-cycle jitter as well as spurs at the internal sampling frequency. because the internal control loop runs at 1 mhz to 2 mhz without regard to the output frequency, output spurs separated from the set frequency by 1 mhz to 2 mhz may be observed. these spurs are characteristically more than 30 db below the level of the set frequency. frequency settling when frequency settings change, the settling time and shape differ depending on which bits are changed. changing only the oct bits will result in an instantaneous change in frequency for oct values below 10. values of 10 and above may take up to 100 s to settle due to the action of internal power conservation circuitry. changing the dac bits will result in a smooth transition between the frequencies, occupying at most 100s, with little overshoot. changing both the oct and dac bits simultaneously may result in considerable excursion beyond the frequencies requested before settling. it should be noted that changing the dac bits at the lower frequency ranges will result in a seemingly instantaneous frequency change because the settling time depends on the internal loop frequency rather than the set frequency. power supply bypass in order to obtain the accuracies represented in this data sheet, it is necessary to provide excellent bypass on the power supply. adequate bypass is a 1 f capacitor in parallel with a 0.01 f capacitor connected within a few millimeters of the power supply leads. monotonicity and linearity the dac in the ltc6903/ltc6904 is guaranteed to be 10-bit monotonic. nonlinearity of the dac is less than 1%. additionally, the ltc6903/ltc6904 is guaranteed to be monotonic when switching between octaves with the oct setting bits. for example, the frequency output with a dac setting of 1111111111 and an oct setting of 1100 will always be lower than the frequency output with a dac setting of 0000000000 and an oct setting of 1101. linearity at these transition points is typically around 3 lsbs. output loading and accuracy improper loading of the outputs of the ltc6903/ltc6904, especially with poor power supply bypassing, will result in accuracy problems. at low frequencies, capacitive loading of the output is not a concern. at frequencies above 1mhz, attention should be paid to minimize the capacitive load on the clk and clk pins. the ltc6903/ltc6904 is designed to drive up to 5 pf on each output with no degradation in accuracy . 5 pf is equivalent to one to two hc series logic inputs. a standard 10x oscilloscope probe usually presents between 10 pf and 15pf of capacitive load. it is strongly suggested that a high speed buffer is used when driving more than one or two logic inputs, when driving a line more than 5 centimeters in length, or a capacitive load greater than 5pf.
ltc6903/ltc6904 10 69034fe applica t ions in f or m a t ion output control the clk and clk outputs of the ltc6903/ltc6904 are individually controllable through the serial port as de- scribed in table 2 below. the low power mode may also be accessed through these control bits. it is preferred that unused outputs be disabled in order to reduce power dissipation and improve accuracy. disabling an unused output will improve accuracy of operation at frequencies above 1mhz. an unused output running with no load typically degrades frequency ac- curacy up to 0.2% at 68 mhz. an unused output running into a 5 pf load typically degrades frequency accuracy up to 0.5% at 68mhz. table 2. output configuration cnf1 cnf0 clk clk 0 0 on clk + 180 0 1 off on 1 0 on off 1 1 powered-down* *powered-down: when in this mode, the chip is in a low power state and will require approximately 100 s to recover. this is not the same effect as the oe pin, which is fast, but uses more power supply current. serial port bitmap (ltc6903/ltc6904) (all serial port register bits default low at power up) table 3 d15 d14 d13 d12 d11 d10 d9 d8 oct3 oct2 oct1 oct0 dac9 dac8 dac7 dac6 d7 d6 d5 d4 d3 d2 d1 d0 dac5 dac4 dac3 dac2 dac1 dac0 cnf1 cnf0 serial port register description oct[3:0] C frequency divider setting. ( see frequency setting information section) dac[9:0] C master oscillator frequency setting. (see frequency setting information section) cnf [1:0] C output configuration. this controls outputs clk and clk according to table 2. ltc6903 spi compatible interface a serial data transfer is composed of sixteen (16) bits of data labeled d15 through d0. d15 is the first bit of data presented in each transaction. all serial port register bits are set low on power-up. writing data (ltc6903 only) when the sen line is brought low, serial data presented on the sdi input is clocked in on the rising edges of sck until sen is brought high. on every eighth rising edge of sck, the preceding 8- bits of data are clocked into the internal register. it is therefore possible to clock in only the 8 {d15 - d8} most significant bits of data rather than completing an entire transfer. the serial data transfer starts with the most significant bit and ends with the least significant bit of the data, as shown in the t iming diagrams section.
ltc6903/ltc6904 11 69034fe applica t ions in f or m a t ion ltc6904 i 2 c interface the ltc6904 communicates with a host ( master) using the standard i 2 c 2- wire interface. the timing diagram shows the timing relationship of the signals on the bus. the two bus lines, sda and scl, must be high when the bus is not in use. external pull-up resistors or current sources, such as the ltc1694 smbus accelerator, are required on these lines. if the i 2 c interface is not driven with a standard i 2 c compatible device, care must be taken to ensure that the sda line is released during the ack cycle to prevent bus contention. the ltc6904 is a receive-only ( slave) device. the master can communicate with the ltc6904 using the write word protocols as explained later. the start and stop conditions when the bus is not in use, both scl and sda must be high. a bus master signals the beginning of a communica- tion to a slave device by transmitting a start condition. a start condition is generated by transitioning sda from high to low while scl is high. when the master has finished communicating with the slave, it issues a stop condition. a stop condition is generated by transitioning sda from low to high while scl is high. the bus is then free for communication with another smbus device. acknowledge the acknowledge signal is used for handshaking between the master and the slave. an acknowledge ( active low) generated by the slave lets the master know that the latest byte of information was received. the acknowledge related clock pulse is generated by the master. the master releases the sda line ( high) during the acknowledge clock pulse. the slave-receiver must pull down the sda line during the acknowledge clock pulse so that it remains a stable low during the high period of this clock pulse. write word protocol the master initiates communication with the ltc6904 with a start condition and a 7- bit address followed by the write bit (wr) = 0. the ltc6904 acknowledges and the master delivers the most significant data byte. again the ltc6904 acknowledges and the data is latched into the most significant data byte input register. the master then delivers the least significant data byte. the ltc6904 acknowledges once more and latches the data into the least significant data byte input register. lastly, the master terminates the communication with a stop condition. slave address the ltc6904 can respond to one of two 7- bit addresses. the first 6 bits ( msbs) have been factory programmed to 001011. the address pin, adr (pin 4) is programmed by the user and determines the lsb of the slave address, as shown in the table below: adr (pin 4) ltc6904 address 0 0010111 1 0010110 write word protocol used by the ltc6904 slave address a wr ms data byte a ls data byte a p s 7 11 8 1 8 69034 f01 1 1 1 s = start condition, wr = write bit = 0, a = acknowledge, p = stop condition
ltc6903/ltc6904 12 69034fe ms8 package 8-lead plastic msop (reference ltc dwg # 05-08-1660 rev f) msop (ms8) 0307 rev f 0.53 0.152 (.021 .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.18 (.007) 0.254 (.010) 1.10 (.043) max 0.22 ? 0.38 (.009 ? .015) typ 0.1016 0.0508 (.004 .002) 0.86 (.034) ref 0.65 (.0256) bsc 0 ? 6 typ detail ?a? detail ?a? gauge plane 12 3 4 4.90 0.152 (.193 .006) 8 7 6 5 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) 0.52 (.0205) ref 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings.
ltc6903/ltc6904 13 69034fe information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number d 12/11 corrected ltc6903 timing diagram. corrected references to frequency setting information section within serial port register description section. 7 10 e 3/12 updated absolute maximum ratings and order information. revised notes 3 and 4 in timing characteristics. 2 4 (revision history begins at rev d)
ltc6903/ltc6904 14 69034fe linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2003 lt 0312 rev e ? printed in usa r ela t e d p ar t s typical a pplica t ion part number description comments ltc1799 1khz to 30mhz thinsot ? oscillator single output, higher frequency operation ltc6900 1khz to 20mhz thinsot oscillator single output, lower power ltc6902 mulitphase oscillator with spread spectrum modulation 1, 3 or 4-phase outputs mux inputs s2 s1 s0 n output pulse width 0 1 0 0 0 1 0 0 0 4 5 6 16/f clk 32/f clk 64/f clk 1 0 1 0 1 0 0 1 0 1 1 1 7 8 9 10 128/f clk 256/f clk 512/f clk 1024/f clk 1 1 1 11 2048/f clk wide range time interval generator (1.97 seconds to 4 microseconds) u6 ltc6903 gnd sdi sck sen 1 2 3 4 trig < trigger pulse width < output pulse width f clk sdi sck sen 8 7 6 5 v + oe clk 69034 ta02 clk 74hc4040 philips semiconductor mux select address lines 7 5 2 13 q8 9 10 11 5 2 8 8 16 16 6 3 4 14 1 q12 12 15 q1 mr clk 6 3 1 4 q q r ps clk d q2 q3 q4 q5 q6 q7 q9 q10 q11 74hc251 philips semiconductor 74hc74-b philips semiconductor 3 1 14 12 s0 4 2 15 13 10 7 11 9 d1 y y d2 d0 d3 d4 d5 d6 d7 s1 s2 oe c3 0.1f v + v out f clk 2 n v out q out c1, 0.1f c2 0.1f 9 12 8 11 6 5 74hc74-a philips semiconductor 13 10 q r ps clk d q 1 output pulse width = u4 u5 u1 f clk s1 s0 s2 v + v + + v v +

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